Si9993CS

Vishay Siliconix

FaxBack 408-970-5600, request 70653

S-60752–Rev. A, 05-Apr-99

www.siliconix.com

11

TABLE 1. Spindle Commutation Sequence

Included on the Si9993CS spindle driver is a unique feedback

circuit which was developed to control the supply current

during the current transfer from one phase of the winding to

another. At the proper time of commutation, the ramping down

of the previous phase is regulated to match with the ramping

up of the next phase, which is fully on initially, until all current

has been transferred to the next phase. This not only reduced

the constraint on power supply requirements but also

eliminated annoying high frequency audible noises generated

from second and third harmonics of the commutation

frequency. The “quiet commutation” operation is a function of

PWM off-time and slew rate control. D7/D4 of REG4 may be

used to optimize the circuit performance accordingly.

System Manager

The

system

manager

includes

power

supply

monitor,

power-on reset timer, individual motor on/off control, system

reference generator and a variety of digital delay timers

targeted for PWM and head retract functions. An external

5-MHz system clock is used mainly for the spindle motor

PWM timing functions. An onboard RC oscillator is used to

generate the timing necessary for the emergency motor

shutdown sequence. When a tight microprocessor power

supply is specified, a pair of external resistors may be used to

Finally, an external capacitor is used to set up the 500-ms

power-on reset pulse for the entire drive electronics. All

controls from the microprocessor or DSP are communicated

via a 16-bit serial port.

Serial Port

A 16-bit word, clocked into the serial interface port of the

Si9993CS, provides the means to program basic operating

conditions, control the motor configuration and to force testing

conditions suitable under the production environment. The

serial port is controlled by three signals IPDATA, IPCLK, and

IPENABLE. The IPDATA signal is the bidirectional data line,

the IPCLK signal is used as the clock to validate the data and

IPENABLE enables serial port operation. This serial port can

be used with the Intel 80C196, AMD 186 processors or other

synchronous serial interfaces.

The serial port allows transfer of a R/W mode bit, seven bits of

register address, and eight bits of data. The port is inactive

when the IPENABLE line is low, and IPCLK must be high.

When IPENABLE is high, the port is active and IPDATA is

strobed on the rising edge of IPCLK. The first bit transferred

on the IPDATA line to the Si9993CS is the R/W mode bit. As

shown in Figure 1, a R/W mode bit of ‘1’ indicates that the

data shall be read from the Si9993CS. Otherwise, the data

shall be written to the Si9993CS as shown in Figure 2. The

next seven bits are the register address. After the transfer of

the address, IPCLK must not switch for a minimum of 70 ns to

allow the IPDATA line to turn around in case of a read

operation. After this pause, one byte of data is transferred to

or from the Si9993CS based on the R/W mode bit. Both the

address and the data are transferred with the LSB first and the

MSB last. IPENABLE must be lowered to deactivate the port

before the next byte can be transferred. Note that Si9993CS’s

six command registers are NOT decoded by unique binary

address. Each register is identified by a specific address bit.

(i.e. an address of 111111 will access all six registers). The

address and function of each command register and the

definition of each bit within the register are shown in Table 2.

Note that unused, or open, bits are handled differently.

For write operation, the unused bits may be either 0 or 1.

For read operation, the first bit to appear at the serial port

is the least significant used bit of the register being read.

Data appearing after the last valid bit should be ignored.

As an example, the data readout sequence for REG1 in

time is D2--D3--D4--D5--D6--D7--X--X.

Emergency Motor Shutdown Sequence

The Si9993CS executes a motor shutdown sequence

whenever a valid low supply condition is detected (i.e. POR

going from High to Low). The circuitry which controls events

within this emergency sequence is powered by spindle

motor’s kinetic energy (BEMF) via the VCLAMP pin. The

critical timing for various events is to be provided by an

onboard RC oscillator and digital counters. The timer’s value

must be programmed by the external microprocessor after the

IC is first powered up. Note that a similar “normal” (nominal

supply) motor shutdown may be invoked by setting D7/D6 of

Sequencer State

HSA

LSA

HSB

LSB

HSC

LSC

Reset*

High

Low

High

Low

High

Low

1

Low

Low

High

High

High

Low

2

Low

Low

High

Low

High

High

3

High

Low

Low

Low

High

High

4

High

High

Low

Low

High

Low

5

High

High

High

Low

Low

Low

6

High

Low

High

High

Low

Low

*Reset is the state after exiting spindle disable or brake mode.

1. Patent Applications Pending