Reading the Conversion Result

EOC is provided to flag the microprocessor when a con-

version is complete. The falling edge of EOC signals

that the data is valid and ready to be output to the bus.

D0–D13 are the parallel outputs of the MAX1065/

MAX1066. These three-state outputs allow for direct

connection to a microcontroller I/O bus. The outputs

remain high-impedance during acquisition and conver-

sion. Data is loaded onto the bus with the third falling

forces the output bus back to high-impedance. The

MAX1065/MAX1066 then waits for the next falling edge

of CS to start the next conversion cycle (Figure 2).

The MAX1065 loads the conversion result onto a 14-bit-

wide data bus while the MAX1066 has a byte-wide out-

put format. HBEN toggles the output between the

most/least significant byte. The least significant byte is

loaded onto the output bus when HBEN is low and the

most significant byte is on the bus when HBEN is high

(Figure 2).

RESET

Toggle RESET with CS high. The next falling edge of

CS will begin acquisition. This reset is an alternative to

the dummy conversion explained in the

Starting a

Conversion section.

Transfer Function

Figure 8 shows the MAX1065/MAX1066 output transfer

function. The output is coded in standard binary.

Input Buffer

Most applications require an input buffer amplifier to

achieve 14-bit accuracy. If the input signal is multiplexed,

the input channel should be switched immediately after

acquisition, rather than near the end of or after a conver-

sion. This allows more time for the input buffer amplifier to

respond to a large step-change in input signal. The input

amplifier must have a high enough slew rate to complete

the required output voltage change before the beginning

of the acquisition time. At the beginning of acquisition, the

internal sampling capacitor array connects to AIN (the

amplifier output) causing some output disturbance.

Ensure that the sampled voltage has settled to within the

required limits before the end of the acquisition time. If

the frequency of interest is low, AIN can be bypassed

with a large enough capacitor to charge the internal sam-

pling capacitor with very little ripple. However, for AC use,

AIN must be driven by a wideband buffer (at least

10MHz), which must be stable with the ADC’s capacitive

load (in parallel with any AIN bypass capacitor used) and

also settle quickly. An example of this circuit using the

MAX4434 is given in Figure 9.

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

______________________________________________________________________________________

11

5V

68k

Ω

100k

Ω

150k

Ω

0.22

μF

REFADJ

MAX1065

MAX1066

Figure 7. MAX1065/MAX1066 Reference Adjust Circuit

ANALOG

INPUT

10

Ω

40pF

AIN

MAX1065/

MAX1066

MAX4434

Figure 9. MAX1065/MAX1066 Fast Settling Input Buffer

OUTPUT CODE

FULL-SCALE

TRANSITION

11...111

12

3

0

FS

FS - 3/2LSB

INPUT VOLTAGE (LSB)

1LSB =

16384

11...110

11...101

00...011

00...010

00...001

00...000

Figure 8. MAX1065/MAX1066 Transfer Function