WM2618

Production Data

WOLFSON MICROELECTRONICS LTD

4

Notes:

1.

Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale

(excluding the effects of zero code and full scale errors).

2.

Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any

adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or

remains constant) as a change in digital input code.

3.

Zero code error is the voltage output when the DAC input code is zero.

4.

Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.

5.

Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this

signal imposed on the zero code error and the gain error.

6.

Zero code error and Gain error temperature coefficients are normalised to full scale voltage.

7.

Output load regulation is the difference between the output voltage at full scale with a 10k

Ω load and 2kΩ load. It

is expressed as a percentage of the full scale output voltage with a 10k

Ω load.

8.

current will increase.

9.

Slew rate results are for the lower value of the rising and falling edge slew rates.

10.

Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising

and falling edges. Limits are ensured by design and characterisation, but are not production tested.

SERIAL INTERFACE

NCS

SCLK

DIN

D15

D14

D13

D12

D11

D0

t

SUCSS

t

WCL

t

WCH

t

SUCS1

t

SUCS2

t

HDCLK

t

SUDCLK

Figure 1 Timing Diagram

Test Conditions:

operating free-air temperature range (unless noted otherwise)

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Setup time NCS low before SCLK low

5ns

Setup time, falling edge of SCLK to rising edge of

NCS, external end of write

10

ns

Setup time, rising edge of SCLK to falling edge of

NCS, start of next write cycle

5ns

Pulse duration, SCLK high

25

ns

Pulse duration, SCLK low

25

ns

Setup time, data ready before SCLK falling edge

5ns

Hold time, data held valid after SCLK falling edge

5ns