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NX2415 Datasheet(PDF) 9 Page - Microsemi Corporation |
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NX2415 Datasheet(HTML) 9 Page - Microsemi Corporation |
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9 / 21 page  NX2415 9 Rev.4.8 05/06/08 Based On Transient Requirement Typically, the output voltage droop during transient is specified as: DROOP TRAN V <V ∆∆ @ step load DI STEP During the transient, the voltage droop during the transient is composed of two sections. One Section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, overshoot caused by DISTEP transient load which is from high load to low load, can be estimated as the following equation,if assuming the bandwidth of system is high enough. 2 OUT overshoot step OUT V V ESRI 2LC ∆ = × ∆ + ×τ ×× ...(6) where τ is the a function of capacitor, etc. EFF crit EFF step OUT EFF crit OUT 0 if LL LI ESR C if LL V ≤ ×∆ τ= − ×≥ ...(7) where OUT EFF OUT OUT EE OUT crit step step L 0.68uH L 0.34uH N2 ESR C V ESRCV L II = == × × ×× == ∆∆ ...(8) where ESR E and CE represents ESR and capaci- tance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected out- put inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and ca- pacitance is high and crit LL ≤ is true. In that case, the transient spec is dependent on the ESR of capacitor. In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be calculated by the following E step 2 OUT tran E tran ESRI V N V 2L CV ×∆ = + ×τ ∆ × × ×∆ ...(9) where EFF crit EFF step E E EFF crit OUT 0 if LL LI ESR C if LL V ≤ ×∆ τ= − ×≥ ...(10) For example, assume voltage droop during transient is 120mV for 30A load step. If the OS-CON capacitors (1000uF, 7m Ω ) is used, the critical inductance is given as EE OUT crit step ESRCV L I 7m 1000 F 1.2V 0.28H 30A ×× == ∆ Ω× µ× =µ The effective inductor value is 0.34uH which is big- ger than critical inductance. In that case, the output volt- age transient not only dependent on the ESR, but also capacitance. number of capacitors is EFF step EE OUT LI ESRC V 0.34 H 30A 7m 1000 F 1.5us 1.2V ×∆ τ = −× µ× = − Ω× µ= E step 2 OUT tran EFF E tran 2 ESRI V N V 2 LCV 7m 30A 120mV 1.2V (1.5us) 2 0.34H 1000 F 120mV 1.78 ×∆ = + ×τ ∆ × × ×∆ Ω× =+ × × µ × µ× = The number of capacitors has to satisfied both ripple and transient requirement. Overall, we can choose N=2. It should be considered that the proposed equa- tion is based on ideal case, in reality, the droop or over- shoot is typically more than the calculation. The equa- tion gives a good start. For more margin, more capaci- tors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP es- pecially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. |
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