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WM8192 Datasheet(PDF) 6 Page - Wolfson Microelectronics plc |
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WM8192 Datasheet(HTML) 6 Page - Wolfson Microelectronics plc |
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6 / 24 page  WM8192 Product Preview WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 6 INPUT VIDEO SAMPLING MCLK VSMP INPUT VIDEO t PER t VSMPSU t VSMPH t VSU t VH t RSU t RH t MCLKL t MCLKH Figure 1 Input Video Timing Note: 1. See Page 14 (Programmable VSMP Detect Circuit) for video sampling description. Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70 °C, MCLK = 12MHz unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS MCLK period tPER 83.3 ns MCLK high period tMCLKH 37.5 ns MCLK low period tMCLKL 37.5 ns VSMP set-up time tVSMPSU 10 ns VSMP hold time tVSMPH 5ns Video level set-up time tVSU 15 ns Video level hold time tVH 5ns Reset level set-up time tRSU 15 ns Reset level hold time tRH 5ns Notes: 1. tVSU and tRSU denote the set-up time required after the input video signal has settled. 2. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK OP[7:0] t PD Figure 2 Output Data Timing |
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