Technical Note

BU4015B,BU4015BF,BU4021B,BU4021BF,

BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B

14/17

www.rohm.com

2009.06 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

1

2

4

5

6

7

14

13

12

9

T1A

CDB

BB

QB

QB

AB

11

3

10

T2B

T2A

CDA

AA

BA

QA

QA

8

VSS

15

T1B

16

VDD

CD

T1

T2

QQ

BA

CD

T1

T2

QQ

BA

CHA

CHB

Block diagram

Truth table

○

Switching characteristics

●

Description of BU4538B series model

Function: Dual high accuracy monostable multivibrator

1) Description of operation

BU4538B is a re-triggerable monostable multi vibrator. Triggering is possible from either edge of the rise time and fall time

of input pulse. Output pulse setting is determined by the time constant (Rx · Cx) of external Rx and Cx.

Recommended output pulse amplitude is 200[μs]~1[s].

(Cautions on use: In case of system power down, etc., electric charge accumulated in the capacity Cx is discharged to the

VDD terminal through protective diode of 2 pins of 14 pins. When the electric current due to accumulated electric charge

exceeds 10[mA], IC may be destructed. When a large capacity Cx is used, electric current flowing into the IC can be

restricted by inserting the diode Dx.)

PIN arrangement

Block diagram

Truth table

PIN description

PIN No. Symbol I/O

Function

1

T1A

―

Passive component

connection pin 1(CHA)

2

T2A

―

Passive component

connection pin 2(CHA)

3

CDA

I

Reset input (CHA)

4

AA

I

Input A(CHA)

5

BA

I

Input B(CHA)

6

QA

O

Output Q(CHA)

7

QAB

O

Output QB(CHA)

8

VSS

―

Power supply(-)

9

QBB

O

Output QB(CHB)

10

QB

O

Output Q(CHB)

11

BB

I

Input B(CHB)

12

AB

I

Input A(CHB)

13

CCB

I

Reset input (CHB)

14

T2B

―

Passive component

connection pin 1(CHB)

15

T1B

―

Passive component

connection pin 2(CHB)

16

VDD

―

Power supply (+)

Vref1

R

S

Q

Q

Q

S

Q

R

Vref2

Enable

Enable

Control

CD

B

A

RX

DX

CX

VDD

VDD

Q

Q

Reset Latch

Output

Latch

A

BCD

OUTPUT

Q

L

HH

H

X：Don't Care

H

HH

H

HL

H

INPUT

L

L

L

Q

H

L

X

8 STAGE

SHIFT REGISTER

CLOCK

SERIAL IN

OUTPUT

ENABLE

8 BIT

LACTH

3 STATE

OUTPUTS

STROBE

Q1

Q8

PARALLEL OUTPUTS

SERIAL

OUTPUT

QS

Q'S

CLOCK

OUTPUT

ENABLE

STROBE

Parallel Output

Qn-1

Q1

Qn

Serial Output

Qs

Q's

Q7

NC

H

Qn-1

Z

Qs

SERIAL

IN

L

X

NC

NC

NC

NC

NC

NC

NC

NC

NC

Q7

Q7

Q7

Z

Z

Z

H

H

H

H

H

H

H

H

H

L

L

L

X

X

X

X

X

Qs

ｔWH

50%

50%

50%

tPHZ

50%

90%

90%

10%

90%

10%

50%

10%

10%

90%

50%

50%

50%

50%

tWL

50%

tPLH

tTLH

tTHL

tPZH

50%

tPLZ

tPZL

tPHL

tpLH

tpLH

ｔsu

ｔh

90%

10%

tr

tf

50%

tPHL

tPLH

tpHL

CLOCK

DATA

STROBE

OUTPUT

ENABLE

Q1～Q7

QS

QS'

Q’S