X22C12

2

PIN DESCRIPTIONS AND DEVICE OPERATION

The address inputs select a 4-bit memory location

during a read or write operation.

Chip Select (

CS)

The Chip Select input must be LOW to enable read or

write operations with the RAM array.

CS HIGH will place

the I/O pins in the high impedance state.

Write Enable (

WE)

The Write Enable input controls the I/O buffers, deter-

mining whether a RAM read or write operation is en-

abled. When

CS is LOW and WE is HIGH, the I/O pins

will output data from the selected RAM address loca-

tions. When both

CS and WE are LOW, data presented

at the I/O pins will be written to the selected address

location.

Data is written to or read from the X22C12 through the

I/O pins. The I/O pins are placed in the high impedance

state when either

CS is HIGH or during either a store or

recall operation.

STORE

The

STORE input, when LOW, will initiate the transfer of

array. The

WE and RECALL inputs are inhibited during

the store cycle. The store operation is completed in 5ms

or less.

A store operation has priority over RAM read/write

operations. If

STORE is asserted during a read opera-

tion, the read will be discontinued. If

STORE is asserted

during a RAM write operation, the write will be immedi-

ately terminated and the store performed. The data at

the RAM address that was being written will be unknown

RECALL

The

RECALL input, when LOW, will initiate the transfer

array. The transfer of data will be completed in 1

µs or

less.

An array recall has priority over RAM read/write opera-

tions and will terminate both operations when

RECALL

is asserted.

RECALL LOW will also inhibit the STORE

input.

Automatic Recall

Upon power-up the X22C12 will automatically recall

Write Protection

The X22C12 has three write protect features that are

employed to protect the contents of the nonvolatile

memory.

<3.5V typical.

• Write Inhibit—Holding either

STORE HIGH or

RECALL LOW during power-up or power-down will

data integrity will be maintained.

• Noise Protection—A

STORE pulse of typically less

than 20ns will not initiate a store cycle.

PIN NAMES

Symbol

Description

Address Inputs

Data Inputs/Outputs

WE

Write Enable

CS

Chip Select

RECALL

Recall

STORE

Store

+5V

Ground

NC

No Connect

3817 PGM T01