X24325PI datasheet(5/17 Pages) XICOR

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X24325

Figure 5. Byte Write

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24325

SLAVE

ADDRESS

WORD

ADDRESS

DATA

6552 ILL F08

DEVICE ADDRESSING

Following a start condition the master must output the

address of the slave it is accessing (see Figure 4). The

next three bits are the device select bits. A system

could have up to eight X24325’s on the bus. The eight

addresses are deﬁned by the state of the S0, S1 and

S2 inputs. S0 and S2 of the slave address must be the

inverse of the S0 and S2 input pins.

Figure 4. Slave Address

The next four bits of the slave address are an exten-

sion of the array’s address and are concatenated with

the eight bits of address in the word address ﬁeld,

providing direct access to the whole 4096 x 8 array.

6552 ILL F07.2

R/W

DEVICE

SELECT

HIGH ORDER

WORD

ADDRESS

A11

A10

The last bit of the slave address deﬁnes the operation to

be performed. When set HIGH a read operation is

selected, when set LOW a write operation is selected.

Following the start condition, the X24325 monitors the

SDA bus comparing the slave address being transmitted

with its slave address device type identiﬁer. Upon a

correct compare the X24325 outputs an acknowledge on

the SDA line. Depending on the state of the R/W bit, the

X24325 will execute a read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24325 requires a second ad-

dress field. This address field is the word address, com-

prised of eight bits, providing access to any one of 4096

words in the array. Upon receipt of the word address, the

X24325 responds with an acknowledge and awaits the

next eight bits of data, again responding with an acknowl-

edge. The master then terminates the transfer by gener-

ating a stop condition, at which time the X24325 begins

the internal write cycle to the nonvolatile memory. While

the internal write cycle is in progress the X24325 inputs

are disabled, and the device will not respond to any re-

quests from the master. Refer to Figure 5 for the address,

acknowledge and data transfer sequence.

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