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X25021 Datasheet(PDF) 1 Page - Xicor Inc.

Part # X25021
Description  SPI Serial E2PROM with Block LockTM Protection
PDF  14 Pages
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Manufacturer  XICOR [Xicor Inc.]
Direct Link  http://www.xicor.com
Logo XICOR - Xicor Inc.

X25021 Datasheet(HTML) 1 Page - Xicor Inc.

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X25021
1
2K
X25021
256 x 8 Bit
©Xicor, Inc. 1995, 1996 Patents Pending
Characteristics subject to change without notice
6615-1.5 6/10/96 T3/C1/D0 NS
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
SPI Serial E2PROM with Block LockTM Protection
FEATURES
• 1MHz Clock Rate
• SPI Modes (0,1 & 1,0)
• 256 X 8 Bits
—4 Byte Page Mode
• Low Power CMOS
—10
µA Standby Current
—3mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
DESCRIPTION
The X25021 is a CMOS 2048-bit serial E2PROM, inter-
nally organized as 256 x 8. The X25021 features a Serial
Peripheral Interface (SPI) and software protocol allow-
ing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (
CS) input, allowing any
number of devices to share the same bus.
The X25021 also features two additional inputs that
provide the end user with added flexibility. By asserting
the
HOLD input, the X25021 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The
WP input can be used as a hardwire input
to the X25021 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.
The X25021 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
6615 FHD F01
FUNCTIONAL DIAGRAM
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
256 BYTE
ARRAY
16 X 32
Y DECODE
DATA REGISTER
16 X 32
32 X 32
SO
SI
SCK
CS
HOLD
WP
16
16
32
8
4
STATUS
REGISTER


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