X25643/45

X25323/25

X25163/65

3

PRINCIPLES OF OPERATION

The device is designed to interface directly with the syn-

chronous Serial Peripheral Interface (SPI) of many popu-

lar microcontroller families.

The device monitors the bus and asserts RESET/RESET

output if there is no bus activity within user programmable

time-out period or the supply voltage falls below a preset

register. It is accessed via the SI input, with data being

clocked in on the rising edge of SCK. CS must be LOW

during the entire operation.

All instructions (Table 1), addresses and data are trans-

ferred MSB first. Data input on the SI line is latched on the

first rising edge of SCK after CS goes LOW. Data is out-

put on the SO line by the falling edge of SCK. SCK is

static, allowing the user to stop the clock and then start it

again to resume operations where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch must

be SET before a Write Operation is initiated. The WREN

instruction will set the latch and the WRDI instruction will

reset the latch (Figure 3). This latch is automatically reset

upon a power-up condition and after the completion of a

valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status Reg-

ister. The Status Register may be read at any time, even

during a Write Cycle. The Status Register is formatted as

follows:

The Write-In-Progress (WIP) bit is a volatile, read only bit

and indicates whether the device is busy with an internal

nonvolatile write operation. The WIP bit is read using the

RDSR instruction. When set to a “1”, a nonvolatile write

operation is in progress. When set to a “0”, no write is in

progress.

The Write Enable Latch (WEL) bit indicates the Status of

the Write Enable Latch. When WEL=1, the latch is set

HIGH and when WEL=0 the latch is reset LOW. The WEL

bit is a volatile, read only bit. It can be set by the WREN

instruction and can be reset by the WRDS instruction.

The Block Lock bits, BL0 and BL1, set the level of Block

grammed using the WRSR instruction and allow the user

to protect one quarter, one half, all or none of the

Protected can be read but not written. It will remain pro-

tected until the BL bits are altered to disable Block Lock

Protection of that portion of memory..

7036 FRM T03

7

6

5

4

3

2

1

0

WPEN

FLB

WD1 WD0

BL1

BL0

WEL

WIP

7036 FRM T02

Status

Register

Bits

Array Addresses Protected

BL1 BL0

X2564x

X2532x

X2516x

0

0

None

None

None

0

1

$1800–$1FFF $0C00–$0FFF $0600–$07FF

1

0

$1000–$1FFF $0800–$0FFF $0400–$07FF

1

1

$0000–$1FFF $0000–$0FFF $0000–$07FF

Table 1. Instruction Set

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

7036 FRM T04

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

SFLB

0000 0000

Set Flag Bit

WRDI/RFLB

0000 0100

Reset the Write Enable Latch/Reset Flag Bit

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

READ

0000 0011

Read Data from Memory Array Beginning at Selected Address

WRITE

0000 0010

Write Data to Memory Array Beginning at Selected Address