X25F047

3

Block Lock Protection

There are eight Block Lock Protection options. The pre-

defined blocks and associated address ranges are pro-

tected by programming the appropriate two byte

Program Status instruction to the device (Table 1 and

Figure 6). Once a Block Lock protect instruction has

been completed, that Block Lock Protection setup is held

in a nonvolatile Status Register (Figure 1) until the next

Program Status instruction is issued. The sections of the

memory array that are Block Lock protected can be read

but not programmed until Block Lock Protection is

removed or changed.

Figure 1. Status Register/Block Lock Protection Byte

Read Sequence

When reading from the SerialFlash memory array, CS is

first pulled LOW to select the device. The 8-bit READ

instruction is transmitted to the X25F047, followed by the

16-bit address, of which the last 9 bits are used (bits

[15:9] specified to be "0’s"). After the READ opcode and

address are sent, the data stored in the memory at the

selected address is shifted out on the SO line. The data

stored in memory at the next address can be read

sequentially by continuing to provide clock pulses. The

address is automatically incremented to the next higher

address after each byte of data is shifted out. When the

highest address is reached (01FFh), the address counter

rolls over to address 0000h, allowing the read cycle to be

continued indefinitely. The read operation is terminated

by taking CS HIGH (Figure 2).

Sector Program Sequence

Prior to any attempt to program data into the X25F047,

the “Program Enable” latch must first be set by issuing

the PREN instruction (Table 1 and Figure 4). CS is first

taken LOW. Then the PREN instruction is clocked into

the X25F047. After all eight bits of the instruction are

transmitted, CS must then be taken HIGH. If the user

continues the program operation without taking CS HIGH

after issuing the PREN instruction, the program opera-

tion will be ignored.

To program data to the SerialFlash memory array, the

user then issues the PROGRAM instruction, followed by

the 16 bit address of the first location in the sector and

then the 16 bytes of data to be programmed. Only the last

9 bits of the address are used and bits [15:9] are speci-

fied to be "0’s". The entire write operation takes 152

clocks. CS must go LOW and remain LOW for the dura-

tion of the operation. The host must program 16 bytes in

each write with the restriction that these bytes reside on

one sector. If the address counter reaches the end of the

sector and the clock continues, or if fewer than 16 bytes

are clocked in, the contents of the sector cannot be guar-

anteed.

For a sector program operation to be completed, CS can

only be brought HIGH after bit 0 of the last data byte to

be programmed is clocked in. If it is brought HIGH at any

other time, the program operation will not be completed.

(Figure 5)

Read Status Operation

If there is not a nonvolatile write in progress, the Read

Status instruction returns the Block Lock Protection byte

from the Status Register which contains the Block Lock

Protection bits BL2-BL0 (Figure 1). The Block Lock Pro-

tection bits define the Block Lock Protection condition

(Figure 1 and Table1). The other bits are reserved and

will return "0’s" when read (Figure 3).

If a nonvolatile write is in progress, the Read Status

instruction returns the status of the internal write opera-

tion on SO. When the nonvolatile write cycle is com-

pleted, the status register data is again read out.

During a nonvolatile write in progress, the SO pin will be

set HIGH. At the end of the nonvolatile write cycle, SO is

set to output the current bit from the status register.

Clocking SCK is valid during a nonvolatile write in

progress, but is not necessary. If the SCK line is clocked,

the pointer to the status register is also clocked, even

though the SO pin shows the status of the nonvolatile

write operation (Figure 3). When the pointer reaches the

end of the eight bit status register, it “rolls over” to the first

bit of the register.

Program Status Operation

Prior to any attempt to perform a Program Status Opera-

tion, the PREN instruction must first be issued. This

instruction sets the “Program Enable” latch and allows

the part to respond to a Program Status sequence (Fig-

ure 6). The Program Status instruction follows and con-

sists of one command byte followed by one Block Lock

Protection byte (Figure 1). This byte contains the Block

Lock Protection bits BL2-BL0. The rest of the bits [7:3]

are unused and must be programmed as “0’s”. Bringing

CS HIGH after the two byte Program Status instruction

initiates a nonvolatile write to the Status Register. Pro-

gramming more than one byte to the Status Register will

overwrite the previously programmed Block Lock Protec-

tion byte (Table 1).

7

6

5

4

3

2

1

0

0

0

0

0

0

BL2

BL1

BL0

Note: Bits [7:3] specified to be “0’s”

7005 FRM T02.1