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Rev.2.02 1/06/2004

SS8039

Applications Information

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, the SS8039H

and SS8039L are relatively immune to short-duration

Figure1 shows typical transient durations, vs. the reset

comparator overdrive, for which both the SS8039H and

SS8039L do not generate a reset pulse. The graph was

starting 0.5V above the actual reset threshold and ending

below it by the magnitude indicated (reset comparator

overdrive). The graph indicates the maximum pulse width

reset pulse. As the magnitude of the transient increases

(goes farther below the reset threshold), the maximum

allowable pulse width decreases. For the SS8039x463

the reset threshold and lasts 15µs or less will not typically

cause a reset pulse. A 0.1µF bypass capacitor mounted

transient immunity.

longer sinks current—it becomes an open circuit.

Therefore, high-impedance CMOS logic inputs con-

nected to RESET can drift to undetermined voltages.

This presents no problem in most applications since

1V. However, in applications where RESET must be

valid down to 0V, adding a pull-down resistor to RESET

causes any stray leakage currents to flow to ground,

holding RESET low (Figure 2). R1’s value is not critical;

100k

Ω is large enough not to load RESET and small

enough to pull RESET to ground.

Benefits of Highly Accurate Reset Threshold

Most µP supervisor ICs have reset threshold voltages

between 5% and 10% below the value of nominal supply

voltages. This ensures a reset will not occur within 5% of

the nominal supply, but will occur when the supply is

10% below nominal.

When using ICs rated at only the nominal supply ±5%,

this leaves a zone of uncertainty where the supply is

between 5% and 10% low, and where the reset may or

may not be asserted.

The SS8039x uses highly accurate circuitry to ensure that

reset is asserted close to the 5% limit, and long before the

supply has declined to 10% below nominal.