X68C64PI datasheet(4/12 Pages) XICOR

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X68C64

MODE SELECTION

Mode

I/O

Power

VSS

Standby

High Z

Standby (CMOS)

LOW

Standby

High Z

Standby (TTL)

HIGH

Read

DOUT

Active

HIGH

LOW

Write

DIN

Active

3868 PGM T02.1

requirements. The rising edge of E starts a timer delay-

ing the internal programming cycle 100

µs. Therefore,

each successive write operation must begin within 100

µs

of the last byte written. The following waveforms illus-

trate the sequence and timing requirements.

PAGE WRITE OPERATION

Regardless of the microcontroller employed, the X68C64

supports page mode write operations. This allows the

microcontroller to write from one to thirty-two bytes of

data to the X68C64. Each individual write within a page

write operation must conform to the byte write timing

Page Write Timing Sequence for E Controlled Operation

Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.

(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page

write operation. Two responses are possible.

a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.

b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a

single memory component as both program and data storage.

3868 FHD F07

tBLC

A/D0–A/D7

A8–A12

R/W

AIN

DIN

A12=n

OPERATION

BYTE 0

BYTE 1

BYTE 2

LAST BYTE

READ (1)(2)

AFTER tWC READY FOR

NEXT WRITE OPERATION

tWC

AIN

DIN

A12=n

AIN

DIN

A12=n

AIN

DIN

A12=n

AIN

DIN

A12=x

AIN

ADDR

AIN

Next Address

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