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X28C256DM Datasheet(PDF) 5 Page - Xicor Inc. |
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X28C256DM Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 24 page  X28C256 5 THE TOGGLE BIT I/O6 Figure 4. Toggle Bit Bus Sequence CE OE WE I/O6 X28C256 READY VOH VOL LAST WRITE HIGH Z * Beginning and ending state of I/O6 will vary. * * 3855 FHD F14 Figure 5. Toggle Bit Software Flow 3855 FHD F15 The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n X28C256 READY COMPARE OK? NO YES LAST WRITE |
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