X28C64DM datasheet(9/25 Pages) XICOR

9 / 25 page

X28C64

SYSTEM CONSIDERATIONS

Because the X28C64 is frequently used in large memory

arrays, it is provided with a two line control architecture

for both read and write operations. Proper usage can

provide the lowest possible power dissipation and elimi-

nate the possibility of contention where multiple I/O pins

share the same bus.

To gain the most benefit it is recommended that

CE be

decoded from the address bus and be used as the

primary device selection input. Both

OE and WE would

then be common among all devices in the array. For a

read operation, this assures that all deselected devices

are in their standby mode and that only the selected

device(s) is outputting data on the bus.

Because the X28C64 has two power modes, standby

and active, proper decoupling of the memory array is of

prime concern. Enabling

CE will cause transient current

spikes. The magnitude of these spikes is dependent on

the output capacitive loading of the I/Os. Therefore, the

larger the array sharing a common bus, the larger the

transient spikes. The voltage peaks associated with the

current transients can be suppressed by the proper

selection and placement of decoupling capacitors. As a

minimum, it is recommended that a 0.1

µF high fre-

quency ceramic capacitor be used between VCC and

VSS at each device. Depending on the size of the array,

the value of the capacitor may have to be larger.

In addition, it is recommended that a 4.7

µF electrolytic

bulk capacitor be placed between VCC and VSS for each

eight devices employed in the array. This bulk capacitor

is employed to overcome the voltage droop caused by

the inductive effects of the PC board traces.

X28C64DM Datasheet(PDF) 9 Page - Xicor Inc.