X88064

2

Pin configuration

PIN NAMES

PIN NAME

I/O

DESCRIPTION

PSEN

I

latched address.

I

Non-multiplexed high-order Address Bus inputs for the upper byte of the address.

I/O

Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a

HIGH to LOW transition.

WR

I

During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is

placed on the bus. The rising edge of

WR latches data into the device.

RD

I

address. Both PSEN an WR signals must be held HIGH during RD controlled read operation.

WC

I

WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order

the last write cycle to the start of internal programming cycle) will inhibit the write operation.

CE

I

The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE

HIGH to LOW transition in order to generate a valid internal device select signal. Holding this

pin HIGH and ALE LOW will place the device in standby mode.

ALE

I

Address Latch Enable input is used to latch the addresses present on the address lines

HIGH to LOW.

7023 FRM F02

NC

NC

NC

WC

PSEN

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

WR

ALE

RD

CE

X88064

DIP/SOIC

Software Data Program Control provides a lower level of

memory write management. SDP controls write opera-

tions to the entire memory. When enabled, the host micro-

processor must send a special 3 byte command sequence

before any byte or page writes to unlocked locations in the

memory.