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XM28C040 Datasheet(PDF) 15 Page - Xicor Inc. |
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XM28C040 Datasheet(HTML) 15 Page - Xicor Inc. |
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15 / 17 page ![]() XM28C040 15 MultiPlane Architecture The design of the XM28C040 has implemented a mul- tiplane architecture. That is, there are four independent 128K x 8 memory spaces or planes, each selected by its own chip enable input via the on-board decoder chip. This architecture can be utilized in a number of ways. Separate Data and Program Memory Spaces The multiplane concept allows the system to write to one plane of the module and still be able to read (continue executing code) from the module, utilizing any plane not performing a write operation. This concept of separate data and program spaces can be expanded by providing a simple off-module circuit that will disable writes to predetermined portions of memory. A very basic version is shown in the Functional Diagram. Whenever A18 is HIGH, the WE input is forced HIGH, write protecting one half the module. This half would be reserved for read only program store while the other half would be available for read and write data store. Expanded Sequential Page Lengths A standard system implementation would be decoding externally the module's chip enable and then wiring each address of the module to its corresponding ad- dress line in the system. This would effectively provide the system a memory organized as four separate memory planes with a sequential page address space of 256 bytes. In an application such as data logging, the most efficient method of logging the data is in a sequential manner. If the data come in bursts that exceed 256 bytes in length a longer page might be desirable. By swapping address lines externally the effective page length can be ex- panded to 1024 bytes. Refer to the table below for a matrix illustrating the various page length options. TABLE 1. ADDRESS TRANSLATION MATRIX Effective A0-A7 A8-A16 A17 A18 Page Size No. of Planes A0-A7 A8-A16 A17 A18 256 4 A0-A7 A9-A17 A8 A18 512 2 A0-A7 A10-A18 A8 A9 1024 1 3873 PGM T09 System Address Lines Module Address Inputs Note: The user should be aware the overall ICC of the module will increase as more individual components on the module are activated. |
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