74AUP2G79_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 30 June 2009

13 of 21

NXP Semiconductors

74AUP2G79

Low-power dual D-type flip-flop; positive-edge trigger

Measurement points are given in Table 9.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 9.

The clock input (nCP) to output (nQ) propagation delays, nCP clock pulse width, nD to nCP set-up times,

nCP to nD hold times and the nCP maximum frequency

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GND

GND

nCP input

nD input

nQ output

Table 9.

Measurement points

Supply voltage

Output

Input

0.8 V to 3.6 V

0.5

0.5

≤ 3.0 ns