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CDC3272G Datasheet(PDF) 2 Page - Micronas |
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CDC3272G Datasheet(HTML) 2 Page - Micronas |
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2 / 2 page ![]() PRODUCT INFORMATION CDC 3272G May/2005 All information and data contained in this product information are without any commitment, are not to be consid- ered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our respective order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH ⋅ Hans-Bunte-Strasse 19 ⋅ D-79108 Freiburg (Germany) ⋅ P.O. Box 840 ⋅ D-79008 Freiburg (Germany) Tel. +49-761-517-0 ⋅ Fax +49-761-517-2174 ⋅ E-mail: docservice@micronas.com ⋅ www.micronas.com No part of this publication may be reproduced, photo- copied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Edition May 18, 2005; Order No. 6251-615-1PI JTAG Probe EVB JTAG JTAG ETM Trace Probe Logic Analyzer Development Tools ◆ Evaluation chip CDC 3205G featuring – ETM via embedded emulation JTAG – ROM/ Flash emulation with external SRAM (up to 8 MBytes) ◆ Evaluation Board (EVB) including the CDC 3205G for evaluation and debug- ging of embedded systems ◆ Application Board (APB) for Flash mem- ory programming ◆ Probe for PQFP128 ◆ Software environment (compiler, linker, assembler) from 3rd party vendors ◆ RTOS from 3rd party vendors ◆ CAN protocol stacks System Architecture The Car Dashboard Controller CDC 3272G contains an embedded ARM7TDMI proces- sor which operates at a maximum clock fre- quency of 50 MHz. The internal high-speed bus connects the following peripherals to the ARM7TDMI pro- cessor: ◆ ICU (Interrupt Control Unit) ◆ SRAM ◆ DMA The 16/32-bit bus connects to the mask ROM. All other peripherals are connected to the I/O bus. All I/O ports have multiple func- tions to obtain utmost flexibility. A total of 102 GPIOs can be selected. The built-in ERM delivers superb EMI results reducing the peak values by up to 10 dB µV. The CDC 3272G is fully pin- and software- compatible with all other members of the CDC 32xxG family. Fig. 2: Block diagram of the CDC 3272G VREFINT VREF AVDD AVSS BVDD UARTS 2 × UART UARTS 2 × SPI UARTS 2 × CAN UARTS DIGITBus UARTS 2 × I²C Bus UARTS LCD Control UARTS Audio Module UARTS Clock Out 0,1 UARTS 16-Bit CCC 0 UARTS UARTS 16-Bit CCC 1 UARTS ARM7TDMI CPU DMA Contr. 40-Input Interrupt Controller 16 KB SRAM Patch Module Bridge Bus Controller P0.6 Comp Wait Comp VDD VSS UVDD UVSS 2.5-V Reg. 2.5-V Reg. 7 × Stepper Motor Module UARTS 1 × 16-Bit Timer UARTS 4 × 8-Bit Timer UARTS 6 × 8/16-Bit PWM 18 52 32 CAPCOM 0,1,2,3 CAPCOM 4,5 PFM0/1 384 KB ROM JTAG Interface Test / Debug Reset Test Watchdog Clock PLL/ERM RTC Power Saving 10-Bit ADC Bandgap Ref. Fig. 1: Development tool setup |
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