AM1705 datasheet(66/155 Pages) TI

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EMB_CS

EMB_CAS

EMB_RAS

EMB_WE

EMB_CLK

EMB_SDCKE

EMB_BA[1:0]

EMB_A[11:0]

EMB_WE_DQM[0]

EMB_WE_DQM[1]

EMB_D[15:0]

EMIFB

CAS

RAS

CLK

CKE

BA[1:0]

A[11:0]

LDQM

UDQM

DQ[15:0]

SDRAM

2Mx16x4

Bank

AM1705

SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010

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6.12.1 Interfacing to SDRAM

The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:

•

Pre-charge bit is A[10]

•

Supports 8, 9, 10 or 11 column address bits

•

Supports up to 13 row address bits

•

Supports 1, 2 or 4 internal banks

Table 6-21 shows the supported SDRAM configurations for EMIFB.

Table 6-21. EMIFB Supported SDRAM Configurations(1)

SDRAM

Memory

Number of

EMIFB Data

Total Memory

Data Bus

Rows

Columns

Banks

Density

Memories

Bus Size

(Mbits)

(Mbytes)

Width

(Mbits)

(bits)

128

256

128

256

128

512

256

128

512

256

1024

128

512

256

1024

128

512

2048

256

1024

(1)

The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of

supporting these densities are not available in the market.

Figure 6-17 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. Figure 6-18

shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 6-22,

as an example that shows additional list of commonly-supported SDRAM devices and the required

connections for the address pins. Note that in Table 6-22, page size/column size (not indicated in the

table) is varied to get the required addressability range.

Figure 6-17. EMIFB to 2M × 16 × 4 bank SDRAM Interface

Peripheral Information and Electrical Specifications

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