ADS1148IPW datasheet(35/50 Pages) TI

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ADS1146

ADS1147

ADS1148

www.ti.com

SBAS453C – JULY 2009 – REVISED APRIL 2010

ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued)

MUX1—Multiplexer Control Register 1

MUX1 - ADDRESS 02h

RESET VALUE = 00h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CLKSTAT

VREFCON1

VREFCON0

REFSELT1

REFSELT0

MUXCAL2

MUXCAL1

MUXCAL0

Bit 7

CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used.

0 = Internal oscillator in use

1 = External oscillator in use

Bits[6:5]

VREFCON[1:0]

These bits control the internal voltage reference. These bits allow the reference to be turned on or

off completely, or allow the reference state to follow the state of the device. Note that the internal

reference is required for operation of the IDAC functions.

00 = Internal reference is always off (default)

01 = Internal reference is always on

10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the

device receives a shutdown opcode or the START pin is taken low

Bits[4:3]

REFSELT[1:0]

These bits select the reference input for the ADC.

00 = REF0 input pair selected (default)

01 = REF1 input pair selected (ADS1148 only)

10 = Onboard reference selected

11 = Onboard reference selected and internally connected to REF0 input pair

Bits[2:0]

MUXCAL[2:0]

These bits are used to select a system monitor. The MUXCAL selection supercedes selections

from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS).

000 = Normal operation (default)

001 = Offset measurement

010 = Gain measurement

011 = Temperature diode

100 = External REF1 measurement (ADS1148 only)

101 = External REF0 measurement

110 = AVDD measurement

111 = DVDD measurement

Table 20 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting

reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset

measurement.

Table 20. MUXCAL Settings

MUXCAL[2:0]

PGA GAIN SETTING

ADC INPUT

000

Set by SYS0 register

Normal operation

001

Set by SYS0 register

Inputs shorted to midsupply (AVDD + AVSS)/2

010

Forced to 1

VREFP – VREFN (full-scale)

011

Forced to 1

Temperature measurement diode

100

Forced to 1

(VREFP1 – VREFN1)/4

101

Forced to 1

(VREFP0 – VREFN0)/4

110

Forced to 1

(AVDD – AVSS)/4

111

Forced to 1

(DVDD – DVSS)/4

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