AM1806 datasheet(61/241 Pages) TI

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AM1806

www.ti.com

SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

5.2

Recommended Operating Conditions

NAME

DESCRIPTION

CONDITION

MIN

NOM

MAX

UNIT

CVDD

Core Logic Supply Voltage (variable)

1.3V operating point

1.25

1.3

1.35

1.2V operating point

1.14

1.2 or 1.26

1.32

1.1V operating point

1.05

1.1

1.16

1.0V operating point

0.95

1.0

1.05

RVDD

Internal RAM Supply Voltage

1.14

1.2 or 1.26

1.32

RTC_CVDD (1)

RTC Core Logic Supply Voltage

0.9

1.2 or 1.26

1.32

PLL0_VDDA

PLL0 Supply Voltage

1.14

1.2 or 1.26

1.32

PLL1_VDDA

PLL1 Supply Voltage

1.14

1.2 or 1.26

1.32

USB_CVDD

USB0 Core Logic Supply Voltage

1.14

1.2 or 1.26

1.32

USB0_VDDA18

USB0 PHY Supply Voltage

1.71

1.8

1.89

USB0_VDDA33

USB0 PHY Supply Voltage

3.15

3.3

3.45

Supply

Voltage

DDR_DVDD18

DDR2 PHY Supply Voltage

1.71

1.8

1.89

0.5*

0.49*

0.51*

DDR_VREF

DDR2/mDDR reference voltage

DDR_DVDD1

DDR_DVDD18

DDR2/mDDR impedance control,

DDR_ZP

Vss

connected via 50

Ω resistor to Vss

1.8V operating point

1.71

1.8

1.89

Power Group A Dual-voltage IO

DVDD3318_A

Supply Voltage

3.3V operating point

3.15

3.3

3.45

1.8V operating point

1.71

1.8

1.89

Power Group B Dual-voltage IO

DVDD3318_B

Supply Voltage

3.3V operating point

3.15

3.3

3.45

1.8V operating point

1.71

1.8

1.89

Power Group C Dual-voltage IO

DVDD3318_C

Supply Voltage

3.3V operating point

3.15

3.3

3.45

Supply

VSS

Core Logic Digital Ground

Ground

PLL0_VSSA

PLL0 Ground

PLL1_VSSA

PLL1 Ground

OSCVSS(2)

Oscillator Ground

RTC_VSS(2)

RTC Oscillator Ground

USB0_VSSA

USB0 PHY Ground

USB0_VSSA33

USB0 PHY Ground

Voltage

VIH

High-level input voltage, Dual-voltage I/O, 3.3V(3)

Input High

High-level input voltage, Dual-voltage I/O, 1.8V (3)

0.65*DVDD

High-level input voltage, RTC_XI

0.8*RTC_CVDD

High-level input voltage, OSCIN

0.8*CVDD

VIL

Low-level input voltage, Dual-voltage I/O, 3.3V(3)

0.8

Voltage

Input Low

Low-level input voltage, Dual-voltage I/O, 1.8V (3)

0.35*DVDD

Low-level input voltage, RTC_XI

0.2*RTC_CVDD

Low-level input voltage, OSCIN

0.2*CVDD

USB

USB0_VBUS

USB external charge pump input

5.25

Transition

Transition time, 10%-90%, All Inputs (unless otherwise

0.25P (4)

Time

specified in the electrical data sections)

(1)

The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered

independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.

If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.

(2)

When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected

directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on

the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.

(3)

These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and

adhere to the JESD79-2A standard.

(4)

Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity

on input signals.

Device Operating Conditions

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