AM1806 datasheet(134/241 Pages) TI

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AM1806

SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

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Table 6-53. Switching Characteristics for McBSP0 [1.0V](1) (2)

(see Figure 6-31)

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from

td(CKSH-CKRXH)

21.5

CLKS input

2P or

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

26.6(3) (4)

(5)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C - 2(6)

C + 2(6)

CLKR int

-4

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR ext

2.5

21.5

CLKX int

-4

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

2.5

21.5

CLKX int

-4

Disable time, DX high impedance following last data bit from CLKX

tdis(CKXH-DXHZ)

high

CLKX ext

-2

21.5

CLKX int

-4 + D1(7)

10 + D2(7)

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

2.5 + D1(7)

21.5 + D2(7)

Delay time, FSX high to DX valid

FSX int

-4(8)

5(8)

td(FXH-DXV)

ONLY applies when in data

FSX ext

-2(8)

21.5(8)

delay 0 (XDATDLY = 00b) mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times

are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4)

P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(5)

Use whichever value is greater.

(6)

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(7)

Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

(8)

Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-54. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V](1) (see Figure 6-31)

1.3V, 1.2V

1.1V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

2P or 20(2) (3)

2P or 25(2) (4)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

P - 1(5)

P - 1(6)

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(3)

Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(4)

Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(5)

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

(6)

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

134

Peripheral Information and Electrical Specifications

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