AM1806 datasheet(143/241 Pages) TI

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AM1806

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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

6.16.2 SPI Electrical Data/Timing

6.16.2.1 Serial Peripheral Interface (SPI) Timing

Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-35

through Figure 6-38).

Table 6-61. General Timing Requirements for SPI0 Master Modes(1)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Cycle Time, SPI0_CLK, All Master

tc(SPC)M

20(2)

256P

30(2)

256P

40(2)

256P

Modes

Pulse Width High, SPI0_CLK, All

tw(SPCH)M

0.5M-1

Master Modes

Pulse Width Low, SPI0_CLK, All

tw(SPCL)M

0.5M-1

Master Modes

Delay,

Polarity = 0, Phase = 0,

initial

to SPI0_CLK rising

data bit

Polarity = 0, Phase = 1,

-0.5M+5

-0.5M+6

valid on

to SPI0_CLK rising

SPI0_SI

td(SIMO_SPC)M

Polarity = 1, Phase = 0,

MO after

to SPI0_CLK falling

initial

edge on

Polarity = 1, Phase = 1,

SPI0_CL

-0.5M+5

-0.5M+6

to SPI0_CLK falling

K(3)

Delay,

Polarity = 0, Phase = 0,

subsequ

from SPI0_CLK rising

ent bits

Polarity = 0, Phase = 1,

valid on

from SPI0_CLK falling

SPI0_SI

td(SPC_SIMO)M

Polarity = 1, Phase = 0,

MO after

from SPI0_CLK falling

transmit

edge of

Polarity = 1, Phase = 1,

SPI0_CL

from SPI0_CLK rising

Output

Polarity = 0, Phase = 0,

0.5M-3

hold

from SPI0_CLK falling

time,

Polarity = 0, Phase = 1,

0.5M-3

SPI0_SI

from SPI0_CLK rising

MO valid

toh(SPC_SIMO)M

Polarity = 1, Phase = 0,

after

0.5M-3

from SPI0_CLK rising

receive

edge of

Polarity = 1, Phase = 1,

SPI0_CL

0.5M-3

from SPI0_CLK falling

Input

Polarity = 0, Phase = 0,

1.5

Setup

to SPI0_CLK falling

Time,

Polarity = 0, Phase = 1,

1.5

SPI0_S

to SPI0_CLK rising

OMI

Polarity = 1, Phase = 0,

tsu(SOMI_SPC)M valid

1.5

to SPI0_CLK rising

before

receive

edge of

Polarity = 1, Phase = 1,

1.5

SPI0_CL to SPI0_CLK falling

(1)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(2)

This timing is limited by the timing shown or 3P, whichever is greater.

(3)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.

Peripheral Information and Electrical Specifications

143

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