AM1806 datasheet(153/241 Pages) TI

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AM1806

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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

Table 6-70. General Timing Requirements for SPI1 Slave Modes(1)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SPC)S

Cycle Time, SPI1_CLK, All Slave Modes

40(2)

256P

50(2)

256P

60(2)

256P

tw(SPCH)S

Pulse Width High, SPI1_CLK, All Slave Modes

tw(SPCL)S

Pulse Width Low, SPI1_CLK, All Slave Modes

Polarity = 0, Phase = 0,

to SPI1_CLK rising

Polarity = 0, Phase = 1,

Setup time, transmit data

to SPI1_CLK rising

written to SPI before initial

tsu(SOMI_SPC)S

clock edge from

Polarity = 1, Phase = 0,

master.(3) (4)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid from SPI1_CLK falling

td(SPC_SOMI)S

on SPI1_SOMI after

Polarity = 1, Phase = 0,

transmit edge of SPI1_CLK

from SPI1_CLK falling

Polarity = 1, Phase = 1,

from SPI1_CLK rising

Polarity = 0, Phase = 0,

0.5S-4

0.5S-10

0.5S-12

from SPI1_CLK falling

Polarity = 0, Phase = 1,

0.5S-4

0.5S-10

0.5S-12

Output hold time,

from SPI1_CLK rising

toh(SPC_SOMI)S

SPI1_SOMI valid after

Polarity = 1, Phase = 0,

receive edge of SPI1_CLK

0.5S-4

0.5S-10

0.5S-12

from SPI1_CLK rising

Polarity = 1, Phase = 1,

0.5S-4

0.5S-10

0.5S-12

from SPI1_CLK falling

Polarity = 0, Phase = 0,

1.5

to SPI1_CLK falling

Polarity = 0, Phase = 1,

1.5

Input Setup Time,

to SPI1_CLK rising

tsu(SIMO_SPC)S

SPI1_SIMO valid before

Polarity = 1, Phase = 0,

receive edge of SPI1_CLK

1.5

to SPI1_CLK rising

Polarity = 1, Phase = 1,

1.5

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time,

from SPI1_CLK rising

tih(SPC_SIMO)S

SPI1_SIMO valid after

Polarity = 1, Phase = 0,

receive edge of SPI1_CLK

from SPI1_CLK rising

Polarity = 1, Phase = 1,

from SPI1_CLK falling

(1)

P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)

(2)

This timing is limited by the timing shown or 3P, whichever is greater.

(3)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.

(4)

Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus

cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Peripheral Information and Electrical Specifications

153

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