TMS320DM335 datasheet(71/155 Pages) TI

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3.5.4.2 USB Clocking

TMS320DM335

Digital Media System-on-Chip (DMSoC)

www.ti.com

SPRS528B – JULY 2008 – REVISED JANUARY 2009

The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of

the USB PHY.

NOTE

For proper USB 2.0 function, SYSCLK2 must be greater than 60 MHz.

The USB PHY takes an input clock that is configurable by the USB PHY clock source bits (PHYCLKSRC)

in the USB PHY control register (USB_PHY_CTL) in the System Control Module. When a 24 MHz crystal

is used at MXI1/MXO1, set PHYCLKSRC to 0. This will present a 24 MHz clock to the USB PHY. When a

36 MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to 1. This will present a 12 MHz clock (36 MHz

divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12

MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1. See the TMS320DM335

Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB) Controller Reference Guide (literature

number SPRUFY9) for more information. See the TMS320DM335 Digital Media System-on-Chip (DMSoC)

ARM Subsystem Reference Guide (literature number SPRUFX7) for more information on the System

Control Module.

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Detailed Device Description

TMS320DM335 Datasheet(PDF) 71 Page - Texas Instruments