TMS320DM355 datasheet(122/159 Pages) TI

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PCLK

(PositiveEdgeClocking)

PCLK

(NegativeEdgeClocking)

7,9

HD/VD

CI[7:0]/YI[7:0]/

CCD[13:0]

8,10

CAM_WEN_FIELD

PCLK

(PositiveEdgeClocking)

CI[7:0]/YI[7:0]/

CCD[13:0]

CAM_WEN_FIELD

PCLK

(PositiveEdgeClocking)

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463F – SEPTEMBER 2007 – REVISED JANUARY 2009

www.ti.com

Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing

Table 5-19. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 5-25)

DM355

NO.

UNIT

MIN

MAX

tsu(CCDV-PCLK)

Setup time, CCD valid before PCLK edge

th(PCLK-CCDV)

Hold time, CCD valid after PCLK edge

tsu(CAM_WEN_FIELD

Setup time, CAM_WEN_FIELD valid before PCLK edge

V-PCLK)

th(PCLK-

Hold time, CAM_WEN_FIELD valid after PCLK edge

CAM_WEN_FIELDV)

(1)

The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the

rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.

Figure 5-25. VPFE (CCD) Master Mode Input Data Timing

122

DM355 Peripheral Information and Electrical Specifications

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TMS320DM355 Datasheet(PDF) 122 Page - Texas Instruments

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