TMS320DM355 datasheet(142/159 Pages) TI

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463F – SEPTEMBER 2007 – REVISED JANUARY 2009

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Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(1)(2)

(see Figure 5-41)

DM355

NO.

PARAMETER

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

38.5 or 2P(3)(4)(5)

td(CLKS-CLKRX)

Delay time, CLKS high to internal CLKR/X

CLKR/X int

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C - 1(6)

C + 1(6)

CLKR int

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR ext

CLKX int

-4

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

CLKX int

tdis(CKXH-

Disable time, DX high impedance following last data

DXHZ)

bit from CLKX high

CLKX ext

CLKX int

-5

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

Delay time, FSX high to DX valid

FSX int

td(FXH-DXV)

ONLY applies when in data

FSX ext

delay 0 (XDATDLY = 00b) mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times

are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4)

P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(5)

Use which ever value is greater.

(6)

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK2, where SYSCLK2 is an output of PLLC1 (see Section 3.5) )

S = sample rate generator input clock = CLKS if CLKSM = 0

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit (see footnote (3) above).

DM355 Peripheral Information and Electrical Specifications

142

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