74LVC2G126GD datasheet(9/17 Pages) NXP

9 / 17 page

74LVC2G126_8

Product data sheet

Rev. 08 — 5 May 2008

9 of 17

NXP Semiconductors

74LVC2G126

Dual bus buffer/line driver; 3-state

Test data is given in Table 10.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 9.

Test circuit for measuring switching times

VEXT

VCC

mna616

DUT

Table 10.

Test data

Supply voltage

Input

Load

VEXT

VCC

tr, tf

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 k

Ω

open

GND

× VCC

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500

Ω

open

GND

× VCC

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

GND

6 V

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

GND

6 V

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500

Ω

open

GND

× VCC

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