74LVC169_5

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 05 — 8 June 2009

13 of 22

NXP Semiconductors

74LVC169

Presettable synchronous 4-bit up/down binary counter

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 8.

Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE)

001aaa654

GND

GND

GND

th

th

tsu

tsu

tsu

th

th

tsu

VM

VM

VM

VI

VI

CP input

PE input

Dn input

VI

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 8.

Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D)

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GND

GND

CP input

CEP, CET, U/D input

Table 8.

Measurement points

Supply voltage

Input

Output

1.2 V

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

1.5 V

1.5 V