CS8427-CSZ datasheet(14/60 Pages) CIRRUS

14 / 60 page

CS8427

DS477F5

clock routing and the associated control register

bits. The clock routing constraints determine which

data routing options are actually usable. Users

should note that not all the possible data flow

switch setting combinations are valid, because of

the clock distribution architecture.

The AESBP switch, shown in Figure 7, allows a

TTL level bi-phase, mark-encoded data stream

connected to RXP to be routed to the TXP and

TXN pin drivers. The TXOFF switch causes the

TXP and TXN outputs to be driven to ground.

There are two possible clock sources. The first,

designated the recovered clock, is the output of the

PLL, and is output through the RMCK pin. The in-

put to the PLL can be either the incoming AES3

data stream or the ILRCK word rate clock from the

serial audio input port. The second clock is input

through the OMCK pin and would normally be a

crystal derived stable clock. The Clock Source

Control Register bits determine which clock is used

to operate the CS8427.

The CS8427 has another constraint related to the

state machine that governs the startup of the part.

The startup state machine doesn’t complete its

process until the PLL has locked unless one is in

the transmitter dataflow (See Figure 10). The con-

sequence of this is that the transmitter will not

transmit until the PLL has locked. If you wish to use

the part in transceiver mode and this constraint is

a problem, there is a work around. Start the part up

in its default configuration and allow the PLL to lock

to a signal on the ILRCK pin, then without stopping

the part, reconfigure it to the transceiver mode.

By studying the following drawings and appropri-

ately setting the Data Flow Control and Clock

Source Control register bits, the CS8427 can be

configured to fit a variety of customer require-

ments. Please note that applications implementing

both the Serial Audio Output Port and the AES3

Transmitter must operate at the same sample rate

because they are both controlled by the same

clock source.

Figure 9 shows the entire data path clocked by the

PLL generated recovered clock. Figure 10 illus-

trates a standard AES3 receiver function. Figure

11 shows a standard AES3 transmitter function

without PLL. Figure 12 shows a standard AES3

transmitter function with PLL.

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