SN54HC595

SN74HC595

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SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009

TIMING REQUIREMENTS

over operating free-air temperature range (unless otherwise noted)

SN54HC595

SN74HC595

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

2 V

6

4.2

5

Clock frequency

4.5 V

31

21

25

MHz

6 V

36

25

29

2 V

80

120

100

SRCLK or RCLK high or low

4.5 V

16

24

20

6 V

14

20

17

Pulse duration

ns

2 V

80

120

100

SRCLR low

4.5 V

16

24

20

6 V

14

20

17

2 V

100

150

125

SER before SRCLK

↑

4.5 V

20

30

25

6 V

17

25

21

2 V

75

113

94

SRCLK

4.5 V

15

23

19

6 V

13

19

16

Setup time

ns

2 V

50

75

65

SRCLR low before RCLK

↑

4.5 V

10

15

13

6 V

9

13

11

2 V

50

75

60

SRCLR high (inactive) before SRCLK

↑

4.5 V

10

15

12

6 V

9

13

11

2 V

0

0

0

Hold time, SER after SRCLK

↑

4.5 V

0

0

0

ns

6 V

0

0

0

(1)

This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case

the shift register is one clock pulse ahead of the storage register.

Copyright © 1982–2009, Texas Instruments Incorporated

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