ISL80102, ISL80103

13

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FN6660.1

March 22, 2010

For additional products, see www.intersil.com/product_tree

frequencies and/or load transient AC output voltage

tolerances.

INPUT CAPACITOR

The minimum input capacitor required for proper

operation is 10µF having a ceramic dielectric. This

ground pins of the LDO with PCB traces no longer than

0.5cm.

Phase Boost Capacitor (Optional)

The ISL80102 and ISL80103 are designed to be stable

with 10µF or larger ceramic capacitor.

Applications using the ADJ versions, may see improved

performance with the addition of a small ceramic

regulation band.

Current Limit Protection

The ISL80102, ISL80103 family of LDOs incorporates

protection against overcurrent due to short, overload

condition applied to the output and the in-rush current

that occurs at start-up. The LDO performs as a constant

current source when the output current exceeds the

current limit threshold noted in the “Electrical

Specifications” table on page 4. If the short or overload

to normal voltage mode regulation. In the event of an

overload condition, the LDO might begin to cycle on and

off due to the die temperature exceeding the thermal

fault condition. The TO220/263 package will tolerate

higher levels of power dissipation on the die which may

never thermal cycle if the heatsink of this larger package

can keep the die temperature below the specified typical

thermal shutdown temperature.

Power Dissipation and Thermals

The junction temperature must not exceed the range

specified in the “Recommended Operating Conditions

(Note 10)” on page 4. The power dissipation can be

calculated by using Equation 3:

and the maximum expected ambient temperature,

dissipation as shown in Equation 4:

resistance.

For safe operation, please make sure that power

The DFN package uses the copper area on the PCB as a

heat-sink. The EPAD of this package must be soldered to

the copper plane (GND plane) for heat sinking. Figure 39

different copper area sizes.

Thermal Fault Protection

In the event the die temperature exceeds typically

+160°C, then the output of the LDO will shut down until

the die temperature can cool down to typically +145°C.

The level of power combined with the thermal impedance

of the package (+48°C/W for DFN) will determine if the

junction temperature exceeds the thermal shutdown

temperature.

P

D

V

IN

V

OUT

–

() I

OUT

V

IN

I

GND

×

+

×

=

(EQ. 3)

P

DMAX

()

T

JMAX

–

() θ

JA

⁄

=

(EQ. 4)

FIGURE 39. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB

COPPER LAND AREA ON PCB

46

44

42

40

38

36

34

2

4

6

8

10

12

14

16

18

20

22

24

EPAD-MOUNT COPPER LAND AREA ON PCB, mm

2

ISL80102, ISL80103