LTC1821 datasheet(9/20 Pages) LINER

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LTC2757

2757f

PIN FUNCTIONS

VOSADJ(Pin39):DACOffsetAdjustPin.Thisvoltage-control

pin can be used to null unipolar offset or bipolar zero error.

The offset change expressed in LSB is the same for any

output range. See

System Offset and Gain Adjustments in

the Operation section. Tie to ground if not used.

IOUT1 (Pin 40): DAC current output; normally tied to the

negative input (summing junction) of the I/V converter

ampliﬁer.

RFB (Pins 41, 42): DAC Feedback Resistor. Normally tied

to the output of the I/V converter ampliﬁer. The DAC output

current from IOUT1 ﬂows through the feedback resistor to

the RFB pins. These pins are internally shorted together.

ROFS (Pins 43, 44): Bipolar Offset Network. These pins

provide the translation of the output voltage range for

bipolar spans. Accepts up to ±15V; normally tied to the

positive reference voltage. These pins are internally shorted

together.

REF (Pins 45, 46): Feedback Resistor for the Reference

Inverting Ampliﬁer, and Reference Input for the DAC.

Normally tied to the output of the reference inverting

ampliﬁer. Typically –5V; accepts up to ±15V. These pins

are internally shorted together.

RCOM (Pin 47): Center Tap Point of RIN and REF. Normally

tied to the negative input of the external reference invert-

ing ampliﬁer.

GEADJ (Pin 48): Gain Adjust Pin. This voltage-control

pin can be used to null gain error or to compensate for

reference errors. The gain error change expressed in LSB

is the same for any output range. See

System Offset and

Gain Adjustments in the Operation section. Tie to ground

if not used.

18-BIT DAC WITH SPAN SELECT

DAC

INPUT

RCOM

RIN

1, 2

20k

ROFS

43, 44

REF

45, 46

RFB

41, 42

IOUT1

VOSADJ

2.56M

IOUT2F

IOUT2S

UPD

READ

D/S

CLR

M-SPAN

2757 BD

CONTROL

LOGIC

I/O

PORT

DAC

INPUT

I/O

PORT

GEADJ

3, 37, 38

SPAN I/O

S2-S0

8-16, 23-31

DATA I/O

D17-D0

BLOCK DIAGRAM

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