CS1500-FSZ datasheet(10/22 Pages) CIRRUS

10 / 22 page

CS1500

DS849A5

May ?$shortyear>

CONFIDENTIAL

or more series elements if voltage breakdown or regulatory

compliance is of concern.

It is recommended that a ceramic capacitor of up to 2.2 nF be

placed between the IAC pin and the VDD pin to filter noise in

the layout.

3.8

Brownout Protection

Figure 17 illustrates the brownout protection mechanism

whereby the CS1500 enters standby, and upon recovery from

brownout, enters normal operation mode. In order to avoid the

fault trigger, a digital filter is added for line voltage detection.

The measured peak of the line voltage will be clamped to a

threshold (128 V) set by the IC within half of a line cycle if it is

higher than the threshold. It then decreases the voltage with a

slew rate of 5 V / trough (8 ms). The CS1500 initiates a timer

when the measured voltage falls below the lower brownout

threshold. The IC asserts the brownout protection and stops

the gate drive only if the timer reaches more than 56 ms,

which is set by the algorithm based on minimum line

frequency.

During the brownout state, the device continues monitoring

the input line voltage. The device exits the brownout state

when the input voltage peak value exceeds the brownout

upper threshold for at least 56 ms.

The maximum response time of the brownout protection

normally happens at light load conditions. It can be calculated

by the following equation:

In the brownout state, the PFC gate driver will restart every 3

seconds, trying to regulate Vlink to nominal value.

Figure 17. Brownout Sequence

3.9

Overpower Protection

During normal operation, if the load is increased beyond the

overpower threshold, the output voltage starts falling. When the

output voltage is below the startup threshold voltage, the CS1500

switches to startup mode and the output voltage will rise back

again to the nominal value and will operate in normal mode if the

load is reduced to a normal level. Otherwise, the PFC oscillates

between startup mode and normal mode and the digital engine

declares the overpower condition. When the overpower

protection is asserted, the IC stops gate drive, goes into a low-

power state, and restarts every 3 seconds. In the case of an

intermittent or minor fault, the device will continue to regulate the

output voltage (Vlink) to its nominal value.

If the PFC remains in startup mode for longer than a given

time, set by the digital controller, it senses an overload

condition and initiates the overpower protection.

The CS1500 has the ability to ensure nearly constant

overpower constraint over a wide range of line voltages, as

shown in Figure 19.

Figure 18. Overpower Protection Mechanism

Figure 19. Maximal Output Power vs. Line Voltage

3.10

Overvoltage Protection

The overvoltage protection will trigger immediately and stop

the gate drive when the current into the FB pin (IOVP) exceeds

105% of the reference current value (Iref). The IC resumes

gate drive switching when the link voltage drops below

VOVP –VOVP(HY).

3.11 Open/short Loop Protection

If the PFC output sense resistor RFB fails (open or short to

GND), the measured output voltage decreases at a slew rate

of about 2V /

μs, which is determined by ADC sampling rate.

The IC stops the gate drive when the measured output voltage

is lower than the measured line voltage. The IC resumes gate

drive switching when the current into the FB pin becomes

larger than or equal to the current into the IAC pin and Vlink is

116.8 ms

[Eq.5]

Brownout

8ms

------------ 128 V

BP th

()

–

() 56 ms

--- 128

–

() 56

56 ms

Start

Timer

Enter Standby

Exit Standby

Upper

Lower

Brownout

Thresholds

Start Timer

TBrownout

t [ms]

Vlink

[V]

100%

90%

t0 + tovrpwr

Overpower

VAC(rms)

265

/ α

L = LB

/ α

L = LB

L < LB

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