GTL2003_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 27 July 2007

5 of 19

NXP Semiconductors

GTL2003

8-bit bidirectional low voltage translator

8.

Application design-in information

8.1 Bidirectional translation

For the bidirectional clamping configuration, higher voltage to lower voltage or lower

voltage to higher voltage, the GREF input must be connected to DREF and both pins

DREF is recommended. The processor output can be totem pole or open-drain (pull-up

resistors may be required) and the chip set output can be totem pole or open-drain

totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs

must be controlled by some direction control mechanism to prevent HIGH-to-LOW

contentions in either direction. If both outputs are open-drain, no direction control is

needed. The opposite side of the reference transistor (SREF) is connected to the

processor core power supply voltage. When DREF is connected through a 200 k

Ω resistor

of each Sn has a maximum output voltage equal to SREF and the output of each Dn has

Typical bidirectional voltage translation.

Fig 4.

application

GREF

DREF

002aac642

D1

D2

200 k

Ω

GTL2002

CHIPSET I/O

5 V

totem pole or

open-drain I/O

GND

SREF

S1

S2

increase bit size

by using 8-bit GTL2003,

10-bit GTL2010,

or 22-bit GTL2000

D3

D4

CHIPSET I/O

D5

Dn

3.3 V

S3

S4

S5

Sn

CPU I/O

1.8 V

1.5 V

1.2 V

1.0 V