P89LPC985FA datasheet(62/85 Pages) NXP

62 / 85 page

P89LPC980_982_983_985_2

Preliminary data sheet

Rev. 02 — 8 February 2010

62 of 85

NXP Semiconductors

P89LPC980/982/983/985

8-bit microcontroller with accelerated two-clock 80C51 core

8.6 Boundary limits interrupt

The ADC has both a high and low boundary limit register. The user may select whether an

interrupt is generated when the conversion result is within (or equal to) the high and low

boundary limits or when the conversion result is outside the boundary limits. An interrupt

will be generated, if enabled, if the result meets the selected interrupt criteria. The

boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be

outside the boundary limits. In this case, after the four MSBs have been converted, these

four bits are compared with the four MSBs of the boundary high and low registers. If the

four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)

an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

criteria, the boundary limits will again be compared after all 8 MSBs have been converted.

A boundary status register (BNDSTA0) flags the channels which caused a boundary

interrupt.

8.7 Clock divider

The ADC requires that its internal clock source be in the range of 500 kHz to 9 MHz to

maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is

provided for this purpose.

8.8 Power-down and Idle mode

In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the A/D interrupt is enabled. In

Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is

enabled, they will consume power. Power can be reduced by disabling the ADC.

P89LPC985FA Datasheet(PDF) 62 Page - NXP Semiconductors