PCA9501_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 10 February 2009

10 of 28

NXP Semiconductors

PCA9501

7.4.2.2

Random read

The PCA9501’s random read mode allows the address to be read from to be specified by

the master. This is done by performing a dummy write to set the address counter to the

location to be read. The master must perform a byte write to the address location to be

read, but instead of transmitting the data after receiving the acknowledge from the

PCA9501, the master re-issues the START condition and memory slave address with the

R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next

eight clock cycles to transmit the data contained in the addressed location. The master

ceases the transmission by issuing the STOP condition after the eighth bit, omitting the

ninth clock cycle acknowledge.

7.4.2.3

Sequential read

The PCA9501 sequential read is an extension of either the current address read or

random read. If the master does not issue a STOP condition after it has received the

eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the

address counter and use the next eight cycles to transmit the data from that location. The

master can continue this process to read the contents of the entire memory. Upon

reaching address 255 the counter will return to address 0 and continue transmitting data

until a STOP condition is received. The master ceases the transmission by issuing the

STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.

Fig 14. Current address read

1

A

S

slave address (memory)

START condition

R/W

acknowledge

from slave

002aad298

data from memory

SDA

A5 A4 A3 A2 A1 A0

1

P

STOP condition

Fig 15. Random read

0

A

S

slave address (memory)

START condition

R/W

acknowledge

from slave

002aad299

word address

SDA

A5 A4 A3 A2 A1 A0

1

P

STOP

condition

A

acknowledge

from slave

data from memory

A

acknowledge

from slave

1

S

slave address (memory)

START condition

R/W

A5 A4 A3 A2 A1 A0

1

Fig 16. Sequential read

1

A

S

slave address (memory)

START condition

R/W

acknowledge

from slave

002aad300

data from memory

SDA

A5 A4 A3 A2 A1 A0

1

P

STOP

condition

A

acknowledge

from master

data from memory

DATA n

data from memory

DATA n + 1

A

acknowledge

from master

DATA n + X