PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

12 of 25

NXP Semiconductors

PCA9502

The register read cycle (see Figure 11) commences in a similar manner, with the master

sending a slave address with the direction bit set to ‘write’ with a following sub-address.

Then, in order to reverse the direction of the transfer, the master issues a repeated START

followed again by the device address, but this time with the direction bit set to ‘read’. The

data bytes starting at the internal sub-address will be clocked out of the device, each

followed by a master-generated acknowledge. The last byte of the read cycle will be

followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated

by a STOP signal.

White block: host to PCA9502

Grey block: PCA9502 to host

Fig 10. Master writes to slave

S

SLAVE ADDRESS

002aab047

W

A

REGISTER ADDRESS

A

nDATA

A

P

White block: host to PCA9502

Grey block: PCA9502 to host

Fig 11. Master read from Slave

S

SLAVE ADDRESS

002aab048

W

A

REGISTER ADDRESS

A

NA

P

S

SLAVE ADDRESS

R

A

nDATA

A

LAST DATA

Table 12.

Bit

Name

Function

7

-

not used

6:3

A[3:0]

internal register select

2:1

-

not used, set to 0

0

-

not used