PCF85133 datasheet(13/41 Pages) NXP

13 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

13 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

7.8 Segment outputs

The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected

directly to the LCD. The segment output signals are generated in accordance with the

multiplexed backplane signals and with data residing in the display register. When less

than 80 segment outputs are required the unused segment outputs must be left

open-circuit.

7.9 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated in accordance with the selected LCD drive mode.

• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same

signals and may also be paired to increase the drive capabilities.

• In static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 80

× 4 bit RAM which stores LCD data. A logic 1 in the RAM

bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0

indicates the off state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs and between the individual bits of a RAM word and

the backplane outputs. The display RAM bit map Figure 9 shows rows 0 to 3 which

correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which

correspond with the segment outputs S0 to S79. In multiplexed LCD applications the

segment data of the ﬁrst, second, third and fourth row of the display RAM are

time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF85133 the received display bytes are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for the acknowledge cycle as with the commands. Depending on

the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets.

To illustrate the ﬁlling order, an example of a 7-segment numeric display showing all drive

modes is given in Figure 10; the RAM ﬁlling organization depicted applies equally to other

LCD types.

The following applies to Figure 10:

• In static drive mode the eight transmitted data bits are placed into row 0 of eight

successive 4-bit RAM words.

• In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

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