ADS6445 datasheet(16/80 Pages) TI

16 / 80 page

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531B – MAY 2007 – REVISED DECEMBER 2009

www.ti.com

Table 11. CFG4 Control Pin

CFG4

DESCRIPTION

0 (default)

MSB First and 2s complement

+ 200mV

(3/6) LVDD

MSB First and offset binary

+/- 200mV

(5/6) LVDD

LSB First and offset binary

+/- 200mV

LVDD

LSB First and 2s complement

- 200mV

SERIAL INTERFACE

The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),

SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial

data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the

the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The

interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with

non-50% duty cycle SCLK.

The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data.

After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:

1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR

2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets

the registers to their default values and then self-resets the <RST> bit to LOW.

When RESET pin is not used, it must be tied to LOW.

Submit Documentation Feedback

Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442

ADS6445 Datasheet(PDF) 16 Page - Texas Instruments