A.C. Characteristics

Symbol

Parameter

Remark

Standard

Mode*

±10%

±10%

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Clock Frequency

¾¾

100

¾

400

¾

1000

kHz

Clock High Time

¾

4000

¾

600

¾

400

¾

ns

Clock Low Time

¾

4700

¾

1200

¾

600

¾

ns

SDA and SCL Rise Time

Note

¾

1000

¾

300

¾

300

ns

SDA and SCL Fall Time

Note

¾

300

¾

300

¾

100

ns

START Condition Hold Time

After this period the first

clock pulse is generated

4000

¾

600

¾

250

¾

ns

START Condition Setup Time

Only relevant for repeated

START condition

4000

¾

600

¾

250

¾

ns

Data Input Hold Time

¾

0

¾

0

¾¾¾

ns

Data Input Setup Time

¾

200

¾

100

¾

100

¾

ns

STOP Condition Setup Time

¾

4000

¾

600

¾

250

¾

ns

Output Valid from Clock

¾¾

3500

¾

900

50

550

ns

Bus Free Time

Time in which the bus must

be free before a new trans-

mission can start

4700

¾

1200

¾

500

¾

ns

Input Filter Time Constant

(SDA and SCL Pins)

Noise suppression time

¾

100

¾

50

¾

50

ns

Write Cycle Time

¾¾

5

¾

5

¾

5ms

Note:

These parameters are periodically sampled but not 100% tested

-40°Cto+85°C

For relative timing, refer to timing diagrams

HT24LC04

Rev. 1.60

3

May 6, 2010

Functional Description

The SCL input is used for positive edge clock data into

each EEPROM device and negative edge clock data

out of each device.

The SDA pin is bidirectional for serial data transfer.

The pin is open-drain driven and may be wired-OR

with any number of other open-drain or open collector

devices.

The HT24LC04 uses the A2 and A1 inputs for hard

wire addressing and a total of four 4K devices may be

addressed on a single bus system. The A0 pin is not

connected. (The device addressing is discussed in

detail under the Device Addressing section).

The HT24LC04 has a write protect pin that provides

hardware data protection. The write protect pin allows

normal read/write operations when connected to the

the write protection feature is enabled and operates

as shown in the following table.

WP Pin Status

Protect Array

Full Array (4K)

Normal Read/Write Operations

Memory Organization

Internally organized with 512 8-bit words, random

word addressing requires a 9-bit data word address.

Device Operations

Data transfer may be initiated only when the bus is not

busy. During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

data line while the clock line is high will be interpreted

as a START or STOP condition.