HT48R52A datasheet(13/35 Pages) HOLTEK

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HT48R52A

Rev. 1.60

April 28, 2010

The states of the registers are summarised in the table.

Reset

(Power On)

WDT Time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

MP0

-xxx xxxx

-uuu uuuu

MP1

-xxx xxxx

-uuu uuuu

ACC

xxxx xxxx

uuuu uuuu

PCL

0000 0000

TBLP

xxxx xxxx

uuuu uuuu

TBLH

--xx xxxx

--uu uuuu

STATUS

--00 xxxx

--1u uuuu

--uu uuuu

--01 uuuu

--11 uuuu

INTC

--00 -000

--uu -uuu

TMR

xxxx xxxx

uuuu uuuu

TMRC

00-0 1000

uu-u uuuu

1111 1111

uuuu uuuu

PAC

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

PBC

1111 1111

uuuu uuuu

0000 0000

uuuu uuuu

1111 1111

uuuu uuuu

1111 1111

uuuu uuuu

MODE

---0 ---0

---u ---u

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

A single Timer/event counter is implemented in the

microcontroller. The timer/event counter contains an 8-bit

programmable count-up counter whose clock may be

sourced from an external source or from the system

clock/4 or fSP.

The fSP clock source is implemented by the WDT OSC,

an external 32768Hz (fRTC) or an instruction clock (sys-

tem clock divided by 4), determined by configuration op-

tion. If one of these three source is selected, it will be

first divided by 16 (4-stage), and then divided by the

TMRC prescaler (8-stage) to get an fSP output period.

By using the TMRC prescaler, longer time-out periods

can be realized. Writing data to PSC2, PSC1, PSC0 can

give different fSP output periods.

Using internal clock sources, there are 2 reference

time-bases for the timer/event counter. The internal

clock source can be sourced from fSYS/4 or fSP via a con-

figuration options. Using an external clock input allows

the user to count external events, measure time

intervals or pulse widths, or generate an accurate time

base, while using the internal clock allows the user to

generate an accurate time base.

There are two registers related to the timer/event coun-

ter; TMR ([0DH]) and TMRC ([0EH]). Two physical reg-

isters are mapped to the TMR register location. Writing

to TMR places the start value in the timer/event counter

preload register while reading the TMR register re-

trieves the contents of the timer/event counter. The

TMRC regiser is a timer/event counter control register

which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source must comes from the ex-

ternal timer pin, TMR. The timer mode functions as a

normal timer with the clock source coming from the fINT

clock. The pulse width measurement mode can be used

to count the duration of a high or low-level signal on the

external timer pin, TMR. The counting is based on the

fINT clock.

In the event count or timer mode, once the timer/event

counter is enabled, it begins counting form the value

placed in the timer/event counter. From this initial value

it will count up to a value of FFH. Once an overflow oc-

curs, the counter is reloaded from the timer/event coun-

ter preload register and at the same time generates the

interrupt request flag, TF; bit 5 of the INTC.

HT48R52A Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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