CDMA Cellular/PCS System

Power Supplies

6

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µs

0.6

Setup Time for STOP Condition

ns

100

Data Setup Time

µs

089

Data Hold Time

µs

0.6

Setup Time Repeated START

Condition

µs

0.6

SCK High Period

µs

1.3

SCK Low Period

µs

0.6

Hold Time Repeated START

Condition

µs

1.3

Bus-Free Time Between START

and STOP

kHz

400

SCK

Clock Frequency

0.6

µA

-1

1

DR1, DR2 OFF Current

(Leakage)

V

0.5

DR1, DR2 Output Low Level

k

Ω

9

19

RSO = 2.48V

RSO Reset Resistance

V

0.5

RSO Output High Level

(Internal Pullup Resistor)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

V

0.5

RSO Output Low Level

V

0.5

ONO Output High Level

V

0.5

ONO Output Low Level

k

Ω

80

360

OFF = 5.5V

OFF Pulldown Resistance

µA

-1

1

0

SCLK (SCK), and CS (AS) only

Logic Input Current

V

0.4

SDA Output Low Level

(MAX1799 only)

V

1.6

Input High Level

V

0.4

Input Low Level

ms

35

110

Watchdog Timer

CONDITIONS

ms

140

430

Reset Timer

ms

175

540

OUT1 Shutdown Timer

(MAX1798A/MAX1799A only)

LOGIC AND CONTROL INPUTS (

ON, OFF, RSO DIN (SDA), SCLK (SCK), CS (AS))

ELECTRICAL CHARACTERISTICS (continued)

open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,