24-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADC

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5

Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.

Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are

removed.

Note 4: Offset nulled.

Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.

Note 6: Noise measured with AIN_+ = AIN_- = AGND.

Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz

sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-

tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not

production tested.

Note 8: Latency is a function of the sampling rate and XIN clock. See the

Latency section in the Digital Filter section.

Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-

ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.

Note 10: Test performed using RXD MP35.

Note 11: All digital inputs at DGND or DVDD.

Note 12:

SYNC is captured by the subsequent XIN clock if this specification is violated.

Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SYNC Pulse Width

tSYN

2

XIN

Clock

Cycles

XIN Clock Pulse Width

tXPW

16

ns

DRDYIN to DRDYOUT

tDRDY

CLOAD = 30pF

20

ns

XIN Clock to

DRDYOUT Delay

tXDRDY

DRDYIN = DGND

40

ns

XIN Clock Period

tXP

40

ns

XIN Clock to

SYNC Setup

tSS

(Note 12)

16

ns

SYNC to XIN Clock Hold

tHS

(Note 12)

5

ns

XIN to CLKOUT Delay

tXCD

40

ns

Power-On Reset Delay

(Note 13)

< 1

ms