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LMP7312MA Datasheet(PDF) 16 Page - National Semiconductor (TI) |
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LMP7312MA Datasheet(HTML) 16 Page - National Semiconductor (TI) |
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16 / 22 page ![]() Gain_0, Gain_1 bit: Gain Values Different gains are available in Attenuation Mode or Amplifi- cation Mode according to the following Gain Table. Gain_1 Gain_0 EN_CL Gain Value (V/V) 0 0 0 0.096 0 1 0 0.192 1 0 0 0.384 1 1 0 0.768 1 0 1 1 1 1 1 2 EN_CL bit: Enable Amplification Mode This register selects which input pair is processed. EN_CL Mode Description 0 Attenuation Mode ±V IN inputs are processed through the 104.16k input resistors 1 Amplification Mode ±IN inputs are processed through the 40k input resistors NULL_SW bit: Input Offset Nulling Switch Mode This register selects a mode in which the amplifier is not pro- cessing any input but it is configured in unity gain to allow system level amplifier offset calibration. The Nulling Switch mode is available in both single ended and fully differential output mode. The LMP7312 in Nulling Switch and fully differ- ential mode has he following configuration. NULL_SW Mode Description 0 Normal Operation Mode ±V IN and ±IN inputs are processed depending on EN_CL register setting. 1 Nulling Switch Mode Enables to evaluate the offset of the internal amplifier for system level calibration 30075507 FIGURE 4. LMP7312 in Nulling Switch Mode In this condition at the Output pins is possible to measure the input voltage offset of the op-amp: Output Mode +V OUT −V OUT/VR Differential V CM_out+VOS/2 V CM_out -VOS/2 Single-Ended V R+VOS V R Hi_Z bit: High Impedance In this mode both outputs +V OUT and -V OUT/VR of the LMP7312 are in tri-state Figure 5. HI_Z Mode Description 0 Normal Operation Mode The LMP7312 is configured according to value of the other 4 bits of the register. 1 High Impedance Mode The LMP7312 output is in high impedance 30075560 FIGURE 5. LMP7312 in High Impedance Mode www.national.com 16 |
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