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LMP8358MA Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LMP8358MA Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 32 page ![]() Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units I TEST Fault Detection: Test Current Setting 1 (CUR[2:0] = 001b), V CM < V + − 2.25V 10 nA Setting 2 (CUR[2:0] = 010b), V CM < V + − 2.25V 100 nA Setting 3 (CUR[2:0] = 011b), V CM < V + − 2.25V 1 µA Setting 4 (CUR[2:0] = 100b), V CM < V + − 2.25V 10 µA Setting 5 (CUR[2:0] = 101b), V CM < V + − 2.25V 100 µA Electrical Characteristics (Serial Interface) Unless otherwise specified, all limits guaranteed for T A = 25°C, V + − V− ≥ 2.7V, V+ ≥ VHSER/VLPAR, V− ≤ VLSER/VHPAR, V D = (VHSER/VLPAR) − (VLSER/VHPAR) ≥ 2.5V. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units V IL Input Logic Low Threshold 0.3 × V D V V IH Input Logic High Threshold 0.7 × V D V V OL Output Logic Low Threshold I SDO = 2mA 0.2 V V OH Output Logic High Threshold I SDO = 2mA V D − 0.2V I SDO Output Source Current, SDO V D = 3.3V or 5.0V, CSB = 0V, V OH = V + – 0.7V −2 mA Output Sink Current, SDO V D = 3.3V or 5.0V, CSB = 0V, V OL = 1.0V 2 I OZ Output Tri-state Leakage Current, SDO V D = 3.3V or 5.0V, CSB = V D = 3.3V or 5V ±1 µA t 1 High Period, SCK (Note 9) 100 ns t 2 Low Period, SCK (Note 9) 100 ns t 3 Set Up Time, CSB to SCK (Note 9) 50 ns t 4 Set Up Time, SDI to SCK (Note 9) 30 ns t 5 Hold Time, SCK to SDI (Note 9) 10 ns t 6 Prop. Delay, SCK to SDO (Note 9) 60 ns t 7 Hold Time, SCK Transition to CSB Rising Edge (Note 9) 50 ns t 8 CSB Inactive (Note 9) 50 ns t 9 Prop. Delay, CSB to SDO Active (Note 9) 50 ns t 10 Prop. Delay, CSB to SDO Inactive (Note 9) 50 ns t 11 Hold Time, SCK Transition to CSB Falling Edge (Note 9) 10 ns t r/tf Signal Rise and Fall Times (Note 9) 1.5 5 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but for which specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of JEDEC). Field- Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC). Note 3: The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can exceed the maximum allowable junction temperature of 150°C. Note 4: The maximum power dissipation is a function of T J(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is P D = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 5: Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: All limits are guaranteed by testing or statistical analysis. 7 www.national.com |
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