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PIC16F785 Datasheet(PDF) 21 Page - Microchip Technology |
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PIC16F785 Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 206 page ![]() © 2008 Microchip Technology Inc. DS41249E-page 19 PIC16F785/HV785 2.2.2.5 PIR1 Register The Peripheral Interrupt Register 1 contains the interrupt flag bits. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REGISTER 1 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE, in the INTCON Register). User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started bit 6 ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 C2IF: Comparator 2 Interrupt Flag bit 1 = Comparator 2 output has changed (must be cleared in software) 0 = Comparator 2 output has not changed bit 3 C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator 1 output has changed (must be cleared in software) 0 = Comparator 1 output has not changed bit 2 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed |
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