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16F648 Datasheet(PDF) 177 Page - Microchip Technology |
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16F648 Datasheet(HTML) 177 Page - Microchip Technology |
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177 / 180 page  © 2009 Microchip Technology Inc. DS40044G-page 177 PIC16F627A/628A/648A Q Q-Clock ............................................................................... 61 Quick-Turnaround-Production (QTP) Devices ...................... 9 R RC Oscillator..................................................................... 101 RC Oscillator Mode Block Diagram........................................................... 101 Reader Response ............................................................. 174 Registers CCP1CON (CCP Operation)....................................... 57 CMCON (Comparator Configuration).......................... 63 CONFIG (Configuration Word).................................... 98 EECON1 (EEPROM Control Register 1) .................... 92 INTCON (Interrupt Control)......................................... 26 Maps PIC16F627A ................................................. 18, 19 PIC16F628A ................................................. 18, 19 OPTION_REG (Option) .............................................. 25 PCON (Power Control) ............................................... 29 PIE1 (Peripheral Interrupt Enable 1)........................... 27 PIR1 (Peripheral Interrupt Register 1) ........................ 28 Status.......................................................................... 24 T1CON Timer1 Control).............................................. 50 T2CON Timer2 Control).............................................. 55 Reset................................................................................. 101 RETFIE Instruction............................................................ 126 RETLW Instruction............................................................ 127 RETURN Instruction ......................................................... 127 Revision History ................................................................ 171 RLF Instruction.................................................................. 127 RRF Instruction ................................................................. 128 S Serial Communication Interface (SCI) Module, See USART Serialized Quick-Turnaround-Production (SQTP) Devices ... 9 SLEEP Instruction............................................................. 128 Software Simulator (MPLAB SIM)..................................... 133 Special Event Trigger. See Compare Special Features of the CPU .............................................. 97 Special Function Registers ................................................. 20 Status Register ................................................................... 24 SUBLW Instruction............................................................ 128 SUBWF Instruction ........................................................... 129 SWAPF Instruction............................................................ 129 T T1CKPS0 bit ....................................................................... 50 T1CKPS1 bit ....................................................................... 50 T1CON Register ................................................................. 50 T1OSCEN bit ...................................................................... 50 T2CKPS0 bit ....................................................................... 55 T2CKPS1 bit ....................................................................... 55 T2CON Register ................................................................. 55 Timer0 Block Diagrams Timer0/WDT ....................................................... 48 External Clock Input.................................................... 47 Interrupt....................................................................... 47 Prescaler..................................................................... 48 Switching Prescaler Assignment................................. 49 Timer0 Module ............................................................ 47 Timer1 Asynchronous Counter Mode ..................................... 52 Capacitor Selection..................................................... 53 External Clock Input ................................................... 51 External Clock Input Timing........................................ 52 Oscillator..................................................................... 53 Prescaler .............................................................. 51, 53 Resetting Timer1 ........................................................ 53 Resetting Timer1 Registers ........................................ 53 Special Event Trigger (CCP) ...................................... 59 Synchronized Counter Mode ...................................... 51 Timer Mode ................................................................ 51 TMR1H ....................................................................... 52 TMR1L........................................................................ 52 Timer2 Block Diagram ............................................................ 54 Postscaler................................................................... 54 PR2 register................................................................ 54 Prescaler .............................................................. 54, 61 Timer2 Module............................................................ 54 TMR2 output............................................................... 54 TMR2 to PR2 Match Interrupt..................................... 60 Timing Diagrams Timer0 ...................................................................... 147 Timer1 ...................................................................... 147 USART Asynchronous Receiver...................................... 83 USART Asynchronous Master Transmission ............. 80 USART Asynchronous Reception .............................. 83 USART Synchronous Reception ................................ 89 USART Synchronous Transmission ........................... 87 Timing Diagrams and Specifications ................................ 144 TMR0 Interrupt.................................................................. 110 TMR1CS bit ........................................................................ 50 TMR1ON bit........................................................................ 50 TMR2ON bit........................................................................ 55 TOUTPS0 bit ...................................................................... 55 TOUTPS1 bit ...................................................................... 55 TOUTPS2 bit ...................................................................... 55 TOUTPS3 bit ...................................................................... 55 TRIS Instruction................................................................ 129 TRISA ................................................................................. 33 TRISB ................................................................................. 38 U Universal Synchronous Asynchronous Receiver Transmitter (USART) ..................................................................... 73 Asynchronous Receiver Setting Up Reception.......................................... 85 Asynchronous Receiver Mode Address Detect ................................................... 85 Block Diagram .................................................... 85 USART Asynchronous Mode................................................... 79 Asynchronous Receiver.............................................. 82 Asynchronous Reception............................................ 84 Asynchronous Transmission ...................................... 80 Asynchronous Transmitter.......................................... 79 Baud Rate Generator (BRG) ...................................... 75 Block Diagrams Transmit.............................................................. 80 USART Receive ................................................. 82 BRGH bit .................................................................... 75 Sampling......................................................... 76, 77, 78 Synchronous Master Mode......................................... 86 Synchronous Master Reception ................................. 88 Synchronous Master Transmission ............................ 86 Synchronous Slave Mode........................................... 89 Synchronous Slave Reception ................................... 90 |
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