16

DS895A2

CS4354

internal reset.

internal reset low, resetting all of the digital circuitry.

Note:

For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-

neously with VA.

4.8

Initialization

When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization

sequence. In this state, the AOUTx pins are weakly pulled to ground and FILT+ is connected to GND.

circuitry is reset and the DAC enters a power-down state until MCLK is applied.

Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-

es the capacitors for the negative voltage supply.

Once LRCK is valid, the number of MCLK cycles is counted relative to the LRCK period to determine the

MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpolation filters

and delta-sigma modulators are turned on, the internal voltage reference, FILT+, powers up to normal op-

eration, the analog output pull-down resistors are removed, and power is applied to the output amplifiers.

If a valid SCLK is applied, the device will clock in data according to the applied SCLK. If no SCLK is present,

the device will clock in data using the derived internal SCLK (see Figure 3 on page 9) and will apply the de-

emphasis filter according to Section 4.4.2.1 on page 14.

After this power-up state sequence is complete, normal operation begins and analog output is generated.

to the analog audio output from AOUTx is less than 50 ms.

See Figure 9 for a diagram of the device’s states and transition conditions.